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this data sheet states amds current technical specifications regarding the products described herein. this data sheet may be revised by subsequent versions or modifications due to changes in technical specifications. publication# 21533 rev: e amendment/ 0 issue date: july 2, 2001 refer to amds website (www.amd.com) for the latest information. am29dl16xd 16 megabit (2 m x 8-bit/1 m x 16-bit) cmos 3.0 volt-only, simultaneous operation flash memory distinctive characteristics architectural advantages n simultaneous read/write operations data can be continuously read from one bank while executing erase/program functions in other bank zero latency between read and write operations n multiple bank architectures four devices available with different bank sizes (refer to table 2) n secsi ? (secured silicon) sector current version of device has 64 kbytes; future versions will have 256 bytes factory locked and identifiable: 16 bytes available for secure, random factory electronic serial number; verifiable as factory locked through autoselect function. expressflash option allows entire sector to be available for factory-secured data customer lockable: can be read, programmed, or erased just like other sectors. once locked, data cannot be changed n zero power operation sophisticated power management circuits reduce power consumed during inactive periods to nearly zero n package options 48-ball fbga 48-pin tsop n top or bottom boot block n manufactured on 0.23 m process technology compatible with am29dl16xc devices n compatible with jedec standards pinout and software compatible with single-power-supply flash standard performance characteristics n high performance access time as fast 70 ns program time: 7 s/word typical utilizing accelerate function n ultra low power consumption (typical values) 2 ma active read current at 1 mhz 10 ma active read current at 5 mhz 200 na in standby or automatic sleep mode n minimum 1 million write cycles guaranteed per sector n 20 year data retention at 125 c reliable operation for the life of the system software features n data management software (dms) amd-supplied software manages data programming and erasing, enabling eeprom emulation eases sector erase limitations n supports common flash memory interface (cfi) n erase suspend/erase resume suspends erase operations to allow programming in same bank n data# polling and toggle bits provides a software method of detecting the status of program or erase cycles n unlock bypass program command reduces overall programming time when issuing multiple program command sequences hardware features n any combination of sectors can be erased n ready/busy# output (ry/by#) hardware method for detecting program or erase cycle completion n hardware reset pin (reset#) hardware method of resetting the internal state machine to reading array data n wp#/acc input pin write protect (wp#) function allows protection of two outermost boot sectors, regardless of sector protect status acceleration (acc) function accelerates program timing n sector protection hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector temporary sector unprotect allows changing data in protected sectors in-system
2 am29dl16xd general description the am29dl16xd family consists of 16 megabit, 3.0 volt-only flash memory devices, organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. word mode data appears on dq0Cdq15; byte mode data appears on dq0Cdq7. the device is designed to be programmed in-system with the standard 3.0 volt v cc supply, and can also be programmed in standard eprom programmers. the device is available with an access time of 70, 90, or 120 ns. the devices are offered in 48-pin tsop and 48-ball fbga packages. standard control pinschip enable (ce#), write enable (we#), and output enable (oe#)control normal read and write operations, and avoid bus contention issues. the device requires only a single 3.0 volt power sup- ply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. simultaneous read/write operations with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into two banks. the device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and simultaneously read from the other bank, with zero la- tency. this releases the system from waiting for the completion of program or erase operations. the am29dl16xd devices uses multiple bank archi- tectures to provide flexibility for different applications. four devices are available with the following bank sizes: am29dl16xd features the secsi ? (secured silicon) sector is an extra sec- tor capable of being permanently locked by amd or customers. the secsi sector indicator bit (dq7) is permanently set to a 1 if the part is factory locked , and set to a 0 if customer lockable . this way, cus- tomer lockable parts can never be used to replace a factory locked part. current version of device has 64 kbytes; future versions will have only 256 bytes. this should be considered during system design. factory locked parts provide several options. the secsi sector may store a secure, random 16 byte esn (electronic serial number), customer code (pro- grammed through amds expressflash service), or both. customer lockable parts may utilize the secsi sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. dms (data management software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of eeprom devices. dms will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. to write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. this is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the flash memory device (or memory de- vices), and more. using dms, user-written software does not need to interface with the flash memory di- rectly. instead, the user's software accesses the flash memory by calling one of only six functions. amd pro- vides this software to simplify system design and software integration efforts. the device offers complete compatibility with the jedec single-power-supply flash command set standard . commands are written to the command register using standard microprocessor write timings. reading data out of the device is similar to reading from other flash or eprom devices. the host system can detect whether a program or erase operation is complete by using the device sta- tus bits: ry/by# pin, dq7 (data# polling) and dq6/dq2 (toggle bits). after a program or erase cycle has been completed, the device automatically returns to reading array data. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. this can be achieved in-system or via programming equipment. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly re- duced in both modes. device bank 1 bank 2 dl161 0.5 mb 15.5 mb dl162 2 mb 14 mb dl163 4 mb 12 mb dl164 8 mb 8 mb
am29dl16xd 3 table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 special handling instructions for fbga package .......................... 6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . 8 device bus operations . . . . . . . . . . . . . . . . . . . . . . 9 table 1. am29dl16xd device bus operations ......................................9 word/byte configuration ................................................................ 9 requirements for reading array data ...........................................9 writing commands/command sequences .................................. 10 accelerated program operation ...............................................10 autoselect functions .................................................................10 simultaneous read/write operations with zero latency ............ 10 standby mode .............................................................................. 10 automatic sleep mode .................................................................10 reset#: hardware reset pin .....................................................11 output disable mode ...................................................................11 table 2. am29dl16xd device bank divisions .....................................11 table 3. sector addresses for top boot sector devices ......................12 table 4. secsi ? sector addresses for top boot devices .................. 12 table 5. sector addresses for bottom boot sector devices .................13 table 6. secsi ? addresses for bottom boot devices ........................ 13 autoselect mode .......................................................................... 14 table 7. am29dl16xd autoselect codes, (high voltage method) ......14 sector/sector block protection and unprotection ........................ 15 table 8. top boot sector/sector block addresses for protection/unprotection ...................................................................15 table 9. bottom boot sector/sector block addresses for protection/unprotection ...................................................................15 write protect (wp#) .....................................................................16 temporary sector/sector block unprotect ................................... 16 figure 1. temporary sector unprotect operation ................................. 16 figure 2. in-system sector/sector block protection and unprotection algorithms ........................................................................ 17 secsi ? (secured silicon) sector flash memory region ............ 18 factory locked: secsi sector programmed and protected at the factory ...................................................................................... 18 customer lockable: secsi sector not programmed or protected at the factory ...........................................................18 hardware data protection ............................................................ 18 low vcc write inhibit ...............................................................19 write pulse glitch protection .................................................. 19 logical inhibit ............................................................................ 19 power-up write inhibit .............................................................. 19 common flash memory interface (cfi) . . . . . . . 19 table 10. cfi query identification string .............................................. 19 table 11. system interface string......................................................... 20 table 12. device geometry definition .................................................. 20 table 13. primary vendor-specific extended query ............................ 21 command definitions . . . . . . . . . . . . . . . . . . . . . . 22 reading array data ...................................................................... 22 reset command .......................................................................... 22 autoselect command sequence .................................................. 22 enter secsi ? sector/exit secsi sector command sequence .... 23 byte/word program command sequence ................................... 23 unlock bypass command sequence .......................................23 figure 3. program operation ................................................................ 24 chip erase command sequence ................................................. 24 sector erase command sequence .............................................. 24 erase suspend/erase resume commands ................................ 25 figure 4. erase operation .................................................................... 25 command definitions ................................................................... 26 table 14. am29dl16xd command definitions .................................... 26 write operation status . . . . . . . . . . . . . . . . . . . . 27 dq7: data# polling ...................................................................... 27 figure 5. data# polling algorithm ......................................................... 27 ry/by#: ready/busy# ................................................................. 28 dq6: toggle bit i .......................................................................... 28 figure 6. toggle bit algorithm .............................................................. 28 dq2: toggle bit ii ......................................................................... 29 reading toggle bits dq6/dq2 .................................................... 29 dq5: exceeded timing limits ...................................................... 29 dq3: sector erase timer ............................................................. 29 table 15. write operation status ......................................................... 30 absolute maximum ratings . . . . . . . . . . . . . . . . 31 figure 7. maximum negative overshoot waveform ............................. 31 figure 8. maximum positive overshoot waveform ............................. 31 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 31 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. i cc1 current vs. time (showing active and automatic sleep currents)..................................................................................... 33 figure 10. typical i cc1 vs. frequency................................................... 33 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11. test setup .......................................................................... 34 table 16. test specifications ................................................................ 34 key to switching waveforms ...................................................... 34 figure 12. input waveforms and measurement levels ........................ 34 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 13. read operation timings...................................................... 35 figure 14. reset timings...................................................................... 36 word/byte configuration (byte#) ............................................... 37 figure 15. byte# timings for read operations .................................. 37 figure 16. byte# timings for write operations .................................. 37 erase and program operations ................................................... 38 figure 17. program operation timings ................................................ 39 figure 18. accelerated program timing diagram ................................ 39 figure 19. chip/sector erase operation timings ................................. 40 figure 20. back-to-back read/write cycle timings ............................. 41 figure 21. data# polling timings (during embedded algorithms) ....... 41 figure 22. toggle bit timings (during embedded algorithms) ............ 42 figure 23. dq2 vs. dq6 ....................................................................... 42 temporary sector/sector block unprotect ................................... 43 figure 24. temporary sector/sector block unprotect timing diagram 43 figure 25. sector/sector block protect and unprotect timing diagram 44 alternate ce# controlled erase and program operations ........... 45 figure 26. alternate ce# controlled write (erase/program) operation timings ................................................................................ 46 erase and programming performance . . . . . . . 47 latchup characteristics . . . . . . . . . . . . . . . . . . . . 47 tsop and so pin capacitance . . . . . . . . . . . . . . 47 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 fbc04848-ball fine-pitch ball grid array (fbga) 8 x 9 mm package ........................................................................ 48 ts 04848-pin standard tsop ................................................. 49 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 50
4 am29dl16xd product selector guide block diagram part number am29dl16xd speed option standard voltage range: v cc = 2.7C3.6 v 70 90 120 max access time (ns) 70 90 120 ce# access (ns) 70 90 120 oe# access (ns) 30 40 50 v cc v ss upper bank address a0Ca19 reset# we# ce# byte# dq0Cdq15 wp#/acc state control & command register ry/by# upper bank x-decoder y-decoder latches and control logic oe# byte# dq0Cdq15 lower bank y-decoder x-decoder latches and control logic lower bank address oe# byte# status control a0Ca19 a0Ca19 a0Ca19 a0Ca19 dq0Cdq15 dq0Cdq15
am29dl16xd 5 connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 nc we# reset# nc wp#/acc ry/by# a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48-pin standard tsop
6 am29dl16xd connection diagrams special handling instructions for fbga package special handling is required for flash memory prod- ucts in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 nc reset# we# dq11 dq3 dq10 dq2 nc a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 48-ball fbga top view, balls facing down
am29dl16xd 7 pin description a0Ca19 = 20 addresses dq0Cdq14 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# = chip enable oe# = output enable we# = write enable wp#/acc = hardware write protect/ acceleration pin reset# = hardware reset pin, active low byte# = selects 8-bit or 16-bit mode ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 20 16 or 8 dq0Cdq15 (a-1) a0Ca19 ce# oe# we# reset# byte# ry/by# wp#/acc
8 am29dl16xd ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. am29dl16xd t 70 e i optional processing blank = standard processing n = 16-byte esn devices temperature range i = industrial (C40 c to +85 c) package type e = 48-pin thin small outline package (tsop) standard pinout (ts 048) wc = 48-ball fine-pitch ball grid array (fbga) 0.80 mm pitch, 8 x 9 mm package (fbc048) speed option see product selector guide and valid combinations boot code sector architecture t= top sector b = bottom sector device number/description am29dl16xd 16 megabit (2 m x 8-bit/1 m x 16-bit) cmos flash memory, 3.0 volt-only read, program, and erase valid combinations for tsop packages am29dl161dt70, am29dl161db70 ei am29dl162dt70, am29dl162db70 am29dl163dt70, am29dl163db70 am29dl164dt70, am29dl164db70 am29dl161dt90, am29dl161db90 am29dl162dt90, am29dl162db90 am29dl163dt90, am29dl163db90 am29dl164dt90, am29dl164db90 am29dl161dt120, am29dl161db120 am29dl162dt120, am29dl162db120 am29dl163dt120, am29dl163db120 am29dl164dt120, am29dl164db120 valid combinations for fbga packages order number package marking am29dl161dt70, am29dl161db70 wci d161dt70v, d161db70v i am29dl162dt70, am29dl162db70 d162dt70v, d162db70v am29dl163dt70, am29dl163db70 d163dt70v, d163db70v am29dl164dt70, am29dl164db70 d164dt70v, d164db70v am29dl161dt90, am29dl161db90 d161dt90v, d161db90v am29dl162dt90, am29dl162db90 d162dt90v, d162db90v am29dl163dt90, am29dl163db90 d163dt90v, d163db90v am29dl164dt90, am29dl164db90 d164dt90v, d164db90v am29dl161dt120, am29dl161db120 d161dt12v, d161db12v am29dl162dt120, am29dl162db120 d162dt12v, d162db12v am29dl163dt120, am29dl163db120 d163dt12v, d163db12v am29dl164dt120, am29dl164db120 d164dt12v, d164db12v
am29dl16xd 9 device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. the contents of the register serve as inputs to the internal state ma- chine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the re- sulting output. the following subsections describe each of these operations in further detail. table 1. am29dl16xd device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 8.5 C12.5 v, v hh = 9.0 0.5 v, x = dont care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are a19:a0 in word mode (byte# = v ih ), a19:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the sector/sector block protection and unprotection section. 3. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in sector/sector block protection and unprotection. if wp#/acc = v hh, all sectors will be unprotected. word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at logic 1, the device is in word con- figuration, dq0Cdq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic 0, the device is in byte configuration, and only data i/o pins dq0Cdq7 are active and controlled by ce# and oe#. the data i/o pins dq8Cdq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the byte# pin determines whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. operation ce# oe# we# reset# wp#/acc addresses (note 2) dq0C dq7 dq8Cdq15 byte# = v ih byte# = v il read l l h h l/h a in d out d out dq8Cdq14 = high-z, dq15 = a-1 write l h l h (note 3) a in d in d in standby v cc 0.3 v xx v cc 0.3 v h x high-z high-z high-z output disable l h h h l/h x high-z high-z high-z reset x x x l l/h x high-z high-z high-z sector protect (note 2) l h l v id l/h sa, a6 = l, a1 = h, a0 = l d in xx sector unprotect (note 2) l h l v id (note 3) sa, a6 = h, a1 = h, a0 = l d in xx temporary sector unprotect x x x v id (note 3) a in d in d in high-z
10 am29dl16xd see requirements for reading array data for more information. refer to the ac read-only operations table for timing specifications and to figure 13 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whether the device accepts program data in bytes or words. refer to word/byte configuration for more information. the device features an unlock bypass mode to facili- tate faster programming. once a bank enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the word/byte configuration section has details on pro- gramming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. tables 3C6 indicate the address space that each sector occupies. the device address space is divided into two banks: bank 1 con- tains the boot/parameter sectors, and bank 2 contains the larger, code sectors of uniform size. a bank ad- dress is the address bits required to uniquely select a bank. similarly, a sector address is the address bits required to uniquely select a sector. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is prima- rily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to nor- mal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated program- ming, or device damage may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7Cdq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose- lect command sequence sections for more information. simultaneous read/write operations with zero latency this device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. an erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. i cc6 and i cc7 in the dc characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device re- quires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when addresses are changed. while in sleep mode, output
am29dl16xd 11 data is latched and always available to the system. i cc4 in the dc characteristics table represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase op- eration, the ry/by# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the sys- tem can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is 1), the reset operation is completed within a time of t ready (not during embedded algo- rithms). the system can read data t rh after the reset# pin returns to v ih . refer to the ac characteristics tables for reset# pa- rameters and to figure 14 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. table 2. am29dl16xd device bank divisions device part number bank 1 bank 2 megabits sector sizes megabits sector sizes am29dl161d 0.5 mbit eight 8 kbyte/4 kword 15.5 mbit thirty-one 64 kbyte/32 kword am29dl162d 2 mbit eight 8 kbyte/4 kword, three 64 kbyte/32 kword 14 mbit twenty-eight 64 kbyte/32 kword am29dl163d 4 mbit eight 8 kbyte/4 kword, seven 64 kbyte/32 kword 12 mbit twenty-four 64 kbyte/32 kword am29dl164d 8 mbit eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword 8 mbit sixteen 64 kbyte/32 kword
12 am29dl16xd table 3. sector addresses for top boot sector devices note: the address range is a19:a-1 in byte mode (byte#=v il ) or a19:a0 in word mode (byte#=v ih ). the bank address bits are a19Ca15 for am29dl161dt, a19Ca17 for am29dl162dt, a19 and a18 for am29dl163dt , and a19 for am29dl164dt. table 4. secsi ? sector addresses for top boot devices am29dl164dt am29dl163dt am29dl162dt am29dl161dt sector sector address a19Ca12 sector size (kbytes/kwords) (x8) address range (x16) address range bank 2 bank 2 bank 2 bank 2 sa0 00000xxx 64/32 000000h-00ffffh 00000hC07fffh sa1 00001xxx 64/32 010000h-01ffffh 08000hC0ffffh sa2 00010xxx 64/32 020000h-02ffffh 10000hC17fffh sa3 00011xxx 64/32 030000h-03ffffh 18000hC1ffffh sa4 00100xxx 64/32 040000h-04ffffh 20000hC27fffh sa5 00101xxx 64/32 050000h-05ffffh 28000hC2ffffh sa6 00110xxx 64/32 060000h-06ffffh 30000hC37fffh sa7 00111xxx 64/32 070000h-07ffffh 38000hC3ffffh sa8 01000xxx 64/32 080000h-08ffffh 40000hC47fffh sa9 01001xxx 64/32 090000h-09ffffh 48000hC4ffffh sa10 01010xxx 64/32 0a0000h-0affffh 50000hC57fffh sa11 01011xxx 64/32 0b0000h-0bffffh 58000hC5ffffh sa12 01100xxx 64/32 0c0000h-0cffffh 60000hC67fffh sa13 01101xxx 64/32 0d0000h-0dffffh 68000hC6ffffh sa14 01110xxx 64/32 0e0000h-0effffh 70000hC77fffh sa15 01111xxx 64/32 0f0000h-0fffffh 78000hC7ffffh bank 1 sa16 10000xxx 64/32 100000h-10ffffh 80000hC87fffh sa17 10001xxx 64/32 110000h-11ffffh 88000hC8ffffh sa18 10010xxx 64/32 120000h-12ffffh 90000hC97fffh sa19 10011xxx 64/32 130000h-13ffffh 98000hC9ffffh sa20 10100xxx 64/32 140000h-14ffffh a0000hCa7fffh sa21 10101xxx 64/32 150000h-15ffffh a8000hCaffffh sa22 10110xxx 64/32 160000h-16ffffh b0000hCb7fffh sa23 10111xxx 64/32 170000h-17ffffh b8000hCbffffh bank 1 sa24 11000xxx 64/32 180000h-18ffffh c0000hCc7fffh sa25 11001xxx 64/32 190000h-19ffffh c8000hCcffffh sa26 11010xxx 64/32 1a0000h-1affffh d0000hCd7fffh sa27 11011xxx 64/32 1b0000h-1bffffh d8000hCdffffh bank 1 sa28 11100xxx 64/32 1c0000h-1cffffh e0000hCe7fffh sa29 11101xxx 64/32 1d0000h-1dffffh e8000hCeffffh sa30 11110xxx 64/32 1e0000h-1effffh f0000hCf7fffh bank 1 sa31 11111000 8/4 1f0000h-1f1fffh f8000hCf8fffh sa32 11111001 8/4 1f2000h-1f3fffh f9000hCf9fffh sa33 11111010 8/4 1f4000h-1f5fffh fa000hCfafffh sa34 11111011 8/4 1f6000h-1f7fffh fb000hCfbfffh sa35 11111100 8/4 1f8000h-1f9fffh fc000hCfcfffh sa36 11111101 8/4 1fa000h-1fbfffh fd000hCfdfffh sa37 11111110 8/4 1fc000h-1fdfffh fe000hCfefffh sa38 11111111 8/4 1fe000h-1fffffh ff000hCfffffh device sector address a19Ca12 sector size (x8) address range (x16) address range am29dl16xdt 11111xxx 64/32 1f0000h-1fffffh f8000hCfffffh
am29dl16xd 13 table 5. sector addresses for bottom boot sector devices note: the address range is a19:a-1 in byte mode (byte#=v il ) or a19:a0 in word mode (byte#=v ih ). the bank address bits are a19Ca15 for am29dl161db, a19Ca17 for am29dl162db, a19 and a18 for am29dl163db , and a19 for am29dl164db. table 6. secsi ? addresses for bottom boot devices am29dl164db am29dl163db am29dl162db am29dl161db sector sector address a19Ca12 sector size (kbytes/kwords) (x8) address range (x16) address range bank 1 bank 1 bank 1 bank 1 sa0 00000000 8/4 000000h-001fffh 00000h-00fffh sa1 00000001 8/4 002000h-003fffh 01000h-01fffh sa2 00000010 8/4 004000h-005fffh 02000h-02fffh sa3 00000011 8/4 006000h-007fffh 03000h-03fffh sa4 00000100 8/4 008000h-009fffh 04000h-04fffh sa5 00000101 8/4 00a000h-00bfffh 05000h-05fffh sa6 00000110 8/4 00c000h-00dfffh 06000h-06fffh sa7 00000111 8/4 00e000h-00ffffh 07000h-07fffh bank 2 sa8 00001xxx 64/32 010000h-01ffffh 08000h-0ffffh sa9 00010xxx 64/32 020000h-02ffffh 10000h-17fffh sa10 00011xxx 64/32 030000h-03ffffh 18000h-1ffffh bank 2 sa11 00100xxx 64/32 040000h-04ffffh 20000h-27fffh sa12 00101xxx 64/32 050000h-05ffffh 28000h-2ffffh sa13 00110xxx 64/32 060000h-06ffffh 30000h-37fffh sa14 00111xxx 64/32 070000h-07ffffh 38000h-3ffffh bank 2 sa15 01000xxx 64/32 080000h-08ffffh 40000h-47fffh sa16 01001xxx 64/32 090000h-09ffffh 48000h-4ffffh sa17 01010xxx 64/32 0a0000h-0affffh 50000h-57fffh sa18 01011xxx 64/32 0b0000h-0bffffh 58000h-5ffffh sa19 01100xxx 64/32 0c0000h-0cffffh 60000h-67fffh sa20 01101xxx 64/32 0d0000h-0dffffh 68000h-6ffffh sa21 01110xxx 64/32 0e0000h-0effffh 70000h-77fffh sa22 01111xxx 64/32 0f0000h-0fffffh 78000h-7ffffh bank 2 sa23 10000xxx 64/32 100000h-10ffffh 80000h-87fffh sa24 10001xxx 64/32 110000h-11ffffh 88000h-8ffffh sa25 10010xxx 64/32 120000h-12ffffh 90000h-97fffh sa26 10011xxx 64/32 130000h-13ffffh 98000h-9ffffh sa27 10100xxx 64/32 140000h-14ffffh a0000h-a7fffh sa28 10101xxx 64/32 150000h-15ffffh a8000h-affffh sa29 10110xxx 64/32 160000h-16ffffh b0000h-b7fffh sa30 10111xxx 64/32 170000h-17ffffh b8000h-bffffh sa31 11000xxx 64/32 180000h-18ffffh c0000h-c7fffh sa32 11001xxx 64/32 190000h-19ffffh c8000h-cffffh sa33 11010xxx 64/32 1a0000h-1affffh d0000h-d7fffh sa34 11011xxx 64/32 1b0000h-1bffffh d8000h-dffffh sa35 11100xxx 64/32 1c0000h-1cffffh e0000h-e7fffh sa36 11101xxx 64/32 1d0000h-1dffffh e8000h-effffh sa37 11110xxx 64/32 1e0000h-1effffh f0000h-f7fffh sa38 11111xxx 64/32 1f0000h-1fffffh f8000h-fffffh device sector address a19Ca12 sector size (x8) address range (x16) address range am29dl16xdb 00000xxx 64/32 000000h-00ffffh 00000h-07fffh
14 am29dl16xd autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7Cdq0. this mode is primarily intended for programming equip- ment to automatically match a device to be programmed with its corresponding programming al- gorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (8.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 7. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see tables 3C6). table 7 shows the remaining address bits that are dont care. when all necessary bits have been set as required, the programming equipment may then read the corre- sponding identifier code on dq7Cdq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 14. this method does not require v id . refer to the autoselect com- mand sequence section for more information. table 7. am29dl16xd autoselect codes, (high voltage method) legend: t = top boot block, b = bottom boot block, l = logic low = v il , h = logic high = v ih , ba = bank address, sa = sector address, x = dont care. description ce# oe# we# a19 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 byte# = v ih byte# = v il manufacturer id : amd l l h ba x v id xlxll x x 01h device id: am29dl161d l l h ba x v id x l x l h 22h x 36h (t), 39h (b) device id: am29dl162d l l h ba x v id x l x l h 22h x 2dh (t), 2eh (b) device id: am29dl163d l l h ba x v id x l x l h 22h x 28h (t), 2bh (b) device id: am29dl164d l l h ba x v id x l x l h 22h x 33h (t), 35h (b) sector protection verification llhsax v id xlxhl x x 01h (protected), 00h (unprotected) secsi ? indicator bit (dq7) llhbax v id xlxhh x x 81h (factory locked), 01h (not factory locked)
am29dl16xd 15 sector/sector block protection and unprotection (note: for the following discussion, the term sector applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see tables 8 and 9). table 8. top boot sector/sector block addresses for protection/unprotection table 9. bottom boot sector/sector block addresses for protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hard- ware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection and unprotection can be im- plemented via two methods. the primary method requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algo- rithms and figure 25 shows the timing diagram. this method uses standard microprocessor bus cycle tim- ing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the sector unprotect algorithm unprotects all sectors in parallel. all previously protected sectors must be in- dividually re-protected. to change data in protected sectors efficiently, the temporary sector unprotect function is available. see temporary sector/sector block unprotect. the alternate method intended only for programming equipment requires v id on address pin a9 and oe#. this method is compatible with programmer routines written for earlier 3.0 volt-only amd flash devices. publication number 22243 contains further details; contact an amd representative to request a copy. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device sector / sector block a19Ca12 sector / sector block size sa0 00000xxx 64 kbytes sa1-sa3 00001xxx, 00010xxx, 00011xxx 192 (3x64) kbytes sa4-sa7 001xxxxx 256 (4x64) kbytes sa8-sa11 010xxxxx 256 (4x64) kbytes sa12-sa15 011xxxxx 256 (4x64) kbytes sa16-sa19 100xxxxx 256 (4x64) kbytes sa20-sa23 101xxxxx 256 (4x64) kbytes sa24-sa27 110xxxxx 256 (4x64) kbytes sa28-sa30 11100xxx, 11101xxx, 11110xxx 192 (3x64) kbytes sa31 11111000 8 kbytes sa32 11111001 8 kbytes sa33 11111010 8 kbytes sa34 11111011 8 kbytes sa35 11111100 8 kbytes sa36 11111101 8 kbytes sa37 11111110 8 kbytes sa38 11111111 8 kbytes sector / sector block a19Ca12 sector / sector block size sa38 11111xxx 64 kbytes sa37-sa35 11110xxx, 11101xxx, 11100xxx 192 (3x64) kbytes sa34-sa31 110xxxxx 256 (4x64) kbytes sa30-sa27 101xxxxx 256 (4x64) kbytes sa26-sa23 100xxxxx 256 (4x64) kbytes sa22-sa19 011xxxxx 256 (4x64) kbytes sa18-sa15 010xxxxx 256 (4x64) kbytes sa14-sa11 001xxxxx 256 (4x64) kbytes sa10-sa8 00001xxx, 00010xxx, 00011xxx 192 (3x64) kbytes sa7 00000111 8 kbytes sa6 00000110 8 kbytes sa5 00000101 8 kbytes sa4 00000100 8 kbytes sa3 00000011 8 kbytes sa2 00000010 8 kbytes sa1 00000001 8 kbytes sa0 00000000 8 kbytes
16 am29dl16xd through amds expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is pro- tected or unprotected. see the autoselect mode section for details. write protect (wp#) the write protect function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the two outermost 8 kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in sector/sector block protection and unprotection. the two outermost 8 kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether the two outermost 8 kbyte boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in sec- tor/sector block protection and unprotection. note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. temporary sector/sector block unprotect (note: for the following discussion, the term sector applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see tables 8 and 9). this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the re- set# pin to v id (8.5 v C 12.5 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously pro- tected sectors are protected again. figure 1 shows the algorithm, and figure 24 shows the timing diagrams, for this feature. figure 1. temporary sector unprotect operation start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected (if wp#/acc = v il , outermost boot sectors will remain protected). 2. all previously protected sectors are protected once again.
am29dl16xd 17 note: the term sector in the figure applies to both sectors and sector blocks. figure 2. in-system sector/sector block protection and unprotection algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 m s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 m s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
18 am29dl16xd secsi ? (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector uses an indicator bit (dq7) to indicate whether or not the sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the secu- rity of the esn once the product is shipped to the field. current version of device has 64 kbytes; future versions will have only 256 bytes. this should be considered during system design. amd offers the device with the secsi sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secsi sector indicator bit permanently set to a 1. the customer-lockable version is shipped with the unprotected, allowing cus- tomers to utilize the that sector in any manner they choose. the customer-lockable version has the secsi sector indicator bit permanently set to a 0. thus, the secsi sector indicator bit prevents customer-lockable devices from being used to replace devices that are factory locked. the system accesses the secsi sector through a command sequence (see enter secsi sector/exit secsi sector command sequence). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the addresses normally occupied by the boot sectors. this mode of operation continues until the system issues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to send- ing commands to the boot sectors. factory locked: secsi sector programmed and protected at the factory in a factory locked device, the secsi sector is pro- tected when the device is shipped from the factory. the secsi sector cannot be modified in any way. the device is available preprogrammed with one of the following: n a random, secure esn only n customer code through the expressflash service n both a random, secure esn and customer code through the expressflash service. in devices that have an esn, a bottom boot device will have the 16-byte esn in the lowest addressable mem- ory area at addresses 00000hC00007h in word mode (or 000000hC00000fh in byte mode). in the top boot device the starting address of the esn will be at the bottom of the lowest 8 kbyte boot sector at addresses f8000hCf8007h in word mode (or 1f0000hC1f000fh in byte mode). customers may opt to have their code programmed by amd through the amd expressflash service. amd programs the customers code, with or without the ran- dom esn. the devices are then shipped from amds factory with the secsi sector permanently locked. contact an amd representative for details on using amds expressflash service. customer lockable: secsi sector not programmed or protected at the factory if the security feature is not required, the secsi sector can be treated as an additional flash memory space, expanding the size of the available flash array. current version of device has 64 kbytes; future versions will have only 256 bytes. this should be consid- ered during system design. the secsi sector can be read, programmed, and erased as often as required. ( note that in upcoming versions of this device, the secsi sector erase function will not be available. ) note that the accelerated programming (acc) and unlock bypass functions are not available when programming the secsi sector. the secsi sector area can be protected using one of the following procedures: n write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. n write the three-cycle enter secsi sector region command sequence, and then use the alternate method of sector protection described in the sec- tor/sector block protection and unprotection. once the secsi sector is locked and verified, the sys- tem must write the exit secsi sector region command sequence to return to reading and writing the remainder of the array. the secsi sector protection must be used with cau- tion since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 14 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by
am29dl16xd 19 spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subse- quent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to reading array data on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the sys- tem can read cfi information at the addresses given in tables 10C13. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 10C13. the system must write the reset command to return the device to the autoselect mode. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/products/nvd/over- view/cfi.html. alternatively, contact an amd representative for copies of these documents. table 10. cfi query identification string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string qry 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists)
20 am29dl16xd table 11. system interface string table 12. device geometry definition addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h v cc min. (write/erase) d7Cd4: volt, d3Cd0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7Cd4: volt, d3Cd0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0004h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses (word mode) addresses (byte mode) data description 27h 4eh 0015h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 58h 0002h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 001eh 0000h 0000h 0001h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information
am29dl16xd 21 table 13. primary vendor-specific extended query note: the number of sectors in bank 2 is device dependent. am29dl161 = 1fh am29dl162 = 1ch am29dl163 = 18h am29dl164 = 10h addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string pri 43h 86h 0031h major version number, ascii 44h 88h 0031h minor version number, ascii 45h 8ah 0000h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 94h 00xxh (see note) simultaneous operation 00 = not supported, x= number of sectors in bank 2 (uniform bank) 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 000xh top/bottom boot sector flag 02h = bottom boot device, 03h = top boot device
22 am29dl16xd command definitions writing specific address and data commands or se- quences into the command register initiates device operations. table 14 defines the valid register com- mand sequences. writing incorrect address and data values or writing them in the improper se- quence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands sec- tion for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations section for more information. the read-only operations table provides the read pa- rameters, and figure 13 shows the timing diagram. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are dont cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys- tem was writing to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the bank to which the system was writing to reading array data. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to read- ing array data (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table 14 shows the address and data requirements. this method is an alternative to that shown in table 7, which is intended for prom programmers and re- quires v id on address pin a9. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the au- toselect command. the bank then enters the autoselect mode. the system may read at any ad- dress within the same bank any number of times without initiating another autoselect command sequence: n a read cycle at address (ba)xx00h (where ba is the bank address) returns the manufacturer code. n a read cycle at address (ba)xx01h in word mode (or (ba)xx02h in byte mode) returns the device code. n a read cycle to an address containing a sector ad- dress (sa) within the same bank, and the address 02h on a7Ca0 in word mode (or the address 04h on a6Ca-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (refer to ta- bles 3C6 for valid sector addresses). the system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in erase suspend).
am29dl16xd 23 enter secsi ? sector/exit secsi sector command sequence the system can access the secsi sector region by is- suing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector command sequence returns the device to nor- mal operation. table 14 shows the address and data requirements for both command sequences. see also secsi sector flash memory region for further infor- mation. note that a hardware reset (reset#=v il ) will reset the device to reading array data. byte/word program command sequence the system may program the device by word or byte, depending on the state of the byte# pin. program- ming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. the program address and data are written next, which in turn initiate the embedded program algo- rithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 14 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, that bank then returns to reading array data and ad- dresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/by#. refer to the write oper- ation status section for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from 0 back to a 1. attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was success- ful. however, a succeeding read will show that the data is still 0. only erase operations can convert a 0 to a 1. unlock bypass command sequence the unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass pro- gram command, a0h; the second cycle contains the program address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. table 14 shows the require- ments for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the reading array data. the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device dam- age may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. figure 3 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 17 for timing diagrams.
24 am29dl16xd figure 3. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 14 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status section for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations tables in the ac characteristics section for parame- ters, and figure 19 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. table 14 shows the ad- dress and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands within the bank may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to reading array data. the system must rewrite the command se- quence and any additional addresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can de- termine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. refer start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 14 for program command sequence.
am29dl16xd 25 to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations tables in the ac characteristics section for parame- ters, and figure 19 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written dur- ing the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a max- imum of 20 s to suspend the erase operation. however, when the erase suspend command is writ- ten during the sector erase time-out, the device immediately terminates the time-out period and sus- pends the erase operation. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device erase sus- pends all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7Cdq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard byte program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is required when writing this command. further writes of the re- sume command are ignored. another erase suspend command can be written after the chip has resumed erasing. figure 4. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 14 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
26 am29dl16xd command definitions table 14. am29dl16xd command definitions legend: x = dont care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a19Ca12 uniquely select any sector. ba = address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15Cdq8 are dont care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a19Ca11 are dont cares. 6. no unlock or command cycles required when bank is reading array data. 7. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address to obtain the manufacturer id, device id, or secsi sector factory protect information. data bits dq15Cdq8 are dont care. see the autoselect command sequence section for more information. 9. the data is 81h for factory locked and 01h for not factory locked. 10. the data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 11. the unlock bypass command is required prior to the unlock bypass program command. 12. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 13. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 14. the erase resume command is valid only during the erase command sequence (note 1) cycles bus cycles (notes 2C5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 (ba)555 90 (ba)x00 01 byte aaa 555 (ba)aaa device id word 4 555 aa 2aa 55 (ba)555 90 (ba)x01 (see table 7) byte aaa 555 (ba)aaa (ba)x02 secsi ? factory protect (note 9) word 4 555 aa 2aa 55 (ba)555 90 (ba)x03 81/01 byte aaa 555 (ba)aaa (ba)x06 sector protect verify (note 10) word 4 555 aa 2aa 55 (ba)555 90 (sa)x02 00/01 byte aaa 555 (ba)aaa (sa)x04 enter secsi sector region word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa exit secsi sector region word 4 555 aa 2aa 55 555 90 xxx 00 byte aaa 555 aaa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 11) 2 xxx a0 pa pd unlock bypass reset (note 12) 2 ba 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 13) 1 ba b0 erase resume (note 14) 1 ba 30 cfi query (note 15) word 1 55 98 byte aa
am29dl16xd 27 write operation status the device provides several bits to determine the sta- tus of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 15 and the following subsec- tions describe the function of these bits. dq7 and dq6 each offer a method for determining whether a pro- gram or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host sys- tem whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to programming during erase suspend. when the em- bedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to reading array data. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the bank returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0Cdq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0Cdq6 may be still invalid. valid data on dq0Cdq7 will appear on suc- cessive read cycles. table 15 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algorithm. figure 21 in the ac characteristics section shows the data# polling timing diagram. figure 5. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?q0 addr = va read dq7?q0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5.
28 am29dl16xd ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is reading array data, the standby mode, or one of the banks is in the erase-sus- pend-read mode. table 15 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase sus- pend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 m s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 15 shows the outputs for toggle bit i on dq6. figure 6 shows the toggle bit algorithm. figure 22 in the ac characteristics section shows the toggle bit timing diagrams. figure 23 shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7Cdq0 toggle bit = toggle? read dq7Cdq0 twice read dq7Cdq0 note: the system should recheck the toggle bit even if dq5 = 1 because the toggle bit may stop toggling as dq5 changes to 1. see the subsections on dq6 and dq2 for more information. figure 6. toggle bit algorithm
am29dl16xd 29 dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 15 to compare out- puts for dq2 and dq6. figure 6 shows the toggle bit algorithm in flowchart form, and the section dq2: toggle bit ii explains the algorithm. see also the dq6: toggle bit i subsection. figure 22 shows the toggle bit timing diagram. figure 23 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6 for the following discussion. when- ever the system initially begins reading toggle bit status, it must read dq7Cdq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7Cdq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it re- turns to determine the status of the operation (top of figure 6). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1, indicating that the program or erase cycle was not successfully completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously pro- grammed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a 1. under both these conditions, the system must write the reset command to return to reading array data (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a 0 to a 1. if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is 1, the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is 0, the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 15 shows the status of dq3 relative to the other status bits.
30 am29dl16xd table 15. write operation status notes: 1. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
am29dl16xd 31 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . C65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . C65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . C0.5 v to +4.0 v a9 , oe# , and reset# (note 2) . . . . . . . . . . . . . . . . . . . . C0.5 v to +12.5 v wp#/acc . . . . . . . . . . . . . . . . . . C0.5 v to +10.5 v all other pins (note 1) . . . . . . C0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 7. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 8. 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is C0.5 v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to C2.0 v for periods of up to 20 ns. see figure 7. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . C40c to +85c v cc supply voltages v cc for standard voltage range . . . . . . . 2.7 v to 3.6 v operating ranges define those limits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.8 v C0.5 v 20 ns C2.0 v figure 7. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 8. maximum positive overshoot waveform
32 am29dl16xd dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 5. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1, 2) ce# = v il, oe# = v ih , byte mode 5 mhz 10 16 ma 1 mhz 2 4 ce# = v il, oe# = v ih , word mode 5 mhz 10 16 1 mhz 2 4 i cc2 v cc active write current (notes 2, 3) ce# = v il, oe# = v ih , we# = v il 15 30 ma i cc3 v cc standby current (note 2) ce#, reset# = v cc 0.3 v 0.2 5 a i cc4 v cc reset current (note 2) reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (notes 2, 4) v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 5 a i cc6 v cc active read-while-program current (notes 1, 2) ce# = v il , oe# = v ih byte 21 45 ma word 21 45 i cc7 v cc active read-while-erase current (notes 1, 2) ce# = v il , oe# = v ih byte 21 45 ma word 21 45 i cc8 v cc active program-while-erase-suspended current (notes 2, 5) ce# = v il , oe# = v ih 17 35 ma i acc acc accelerated program current, word or byte ce# = v il , oe# = v ih acc pin 5 10 ma v cc pin 15 30 ma v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v hh voltage for wp#/acc sector protect/unprotect and program acceleration v cc = 3.0 v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 8.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = C2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = C100 a, v cc = v cc min v cc C0.4 v lko low v cc lock-out voltage (note 5) 2.3 2.5 v
am29dl16xd 33 dc characteristics zero-power flash note: addresses are switching at 1 mhz figure 9. i cc1 current vs. time (showing active and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 12345 frequency in mhz supply current in ma note: t = 25 c figure 10. typical i cc1 vs. frequency 2.7 v 3.6 v 4 6 12
34 am29dl16xd test conditions table 16. test specifications key to switching waveforms 2.7 k w c l 6.2 k w 3.3 v device under te s t note: diodes are in3064 or equivalent figure 11. test setup test condition 70, 80 90, 120 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0C3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v waveform inputs outputs steady changing from h to l changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 12. input waveforms and measurement levels
am29dl16xd 35 ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 11 and table 16 for test specifications. 3. measurements performed by placing a 50-ohm termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . parameter description test setup speed options jedec std 70 80 90 120 unit t avav t rc read cycle time (note 1) min 70 80 90 120 ns t avqv t acc address to output delay ce#, oe# = v il max 70 80 90 120 ns t elqv t ce chip enable to output delay oe# = v il max 70 80 90 120 ns t glqv t oe output enable to output delay max 30 30 40 50 ns t ehqz t df chip enable to output high z (notes 1, 3) max 16 16 16 16 ns t ghqz t df output enable to output high z (notes 1, 3) max 16 16 16 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df figure 13. read operation timings
36 am29dl16xd ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 m s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 m s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 14. reset timings
am29dl16xd 37 ac characteristics word/byte configuration (byte#) parameter speed options jedec std description 70 80 90 120 unit t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 25 25 30 30 ns t fhqv byte# switching high to output active min 70 80 90 120 ns dq15 output data output (dq0Cdq7) ce# oe# byte# t elfl dq0Cdq14 data output (dq0Cdq14) dq15/a-1 address input t flqz byte# switching from word to byte mode dq15 output data output (dq0Cdq7) byte# t elfh dq0Cdq14 data output (dq0Cdq14) dq15/a-1 address input t fhqv byte# switching from byte to word mode figure 15. byte# timings for read operations note: refer to the erase/program operations table for t as and t ah specifications. figure 16. byte# timings for write operations ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
38 am29dl16xd ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. parameter speed options jedec std description 70 80 90 120 unit t avav t wc write cycle time (note 1) min 70 80 90 120 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min15151515ns t wlax t ah address hold time min 45 45 45 50 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 35 45 50 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 20 20 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 30 30 35 50 ns t whdl t wph write pulse width high min 30 30 30 30 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) byte typ 5 s word typ 7 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) ty p 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay min 90 ns
am29dl16xd 39 ac characteristics figure 18. accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. figure 17. program operation timings wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
40 am29dl16xd ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sa = sector address (for sector erase), va = valid address for reading status data ( see write operation status). 2 . these waveforms are for the word mode. figure 19. chip/sector erase operation timings
am29dl16xd 41 ac characteristics oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w figure 20. back-to-back read/write cycle timings we# ce# oe# high z t oe high z dq7 dq0Cdq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 21. data# polling timings (during embedded algorithms)
42 am29dl16xd ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 22. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 23. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
am29dl16xd 43 ac characteristics temporary sector/sector block unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector/sector block unprotect min 4 m s t rrb reset# hold time from ry/by# high for temporary sector/sector block unprotect min 4 m s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 24. temporary sector/sector block unprotect timing diagram
44 am29dl16xd ac characteristics sector/sector block protect: 150 s, sector/sector block unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector/sector block protect or unprotect verify v id v ih * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. figure 25. sector/sector block protect and unprotect timing diagram
am29dl16xd 45 ac characteristics alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. parameter speed options jedec std description 70 80 90 120 unit t avav t wc write cycle time (note 1) min 70 80 90 120 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 45 45 50 ns t dveh t ds data setup time min 35 35 45 50 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 30 30 45 50 ns t ehel t cph ce# pulse width high min 30 30 30 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 5 s word typ 7 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) ty p 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec
46 am29dl16xd ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 26. alternate ce# controlled write (erase/program) operation timings
am29dl16xd 47 erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90 c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 14 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1,000,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. tsop and so pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 15 sec excludes 00h programming prior to erasure (note 4) chip erase time 27 sec byte program time 5 150 s excludes system level overhead (note 5) word program time 7 210 s accelerated byte/word program time 4 120 s chip program time (note 3) byte mode 9 27 sec word mode 6 18 description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) C1.0 v 12.5 v input voltage with respect to v ss on all i/o pins C1.0 v v cc + 1.0 v v cc current C100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf parameter description test conditions min unit minimum pattern data retention time 150 c 10 years 125 c 20 years
48 am29dl16xd physical dimensions fbc04848-ball fine-pitch ball grid array (fbga) 8 x 9 mm package dwg rev af; 10/99
am29dl16xd 49 physical dimensions ts 04848-pin standard tsop dwg rev aa; 10/99
50 am29dl16xd revision summary revision a (september 1998) initial release. revision b (october 1998) global deleted the 90r and 120r speed options. expanded the full voltage range to 2.7C3.6 v. distinctive characteristics added 125 c to 20-year data retention bullet. connection diagrams changed the fbga diagram from bottom view to top view. ordering information changed the fbga ordering nomenclature to yc. the package designation is now fbc048. reverted to wc in revision c. dc characteristics changed maximum i li current to 3.0 a. physical dimensions updated the fbga drawing, table, and notes. the package designation is now fbc048. deleted 40-pin tsop drawing. revision b+1 (october 1998) command definitions table added the term sector block to the notes where appropriate. dc characteristics changed maximum i li current to 1.0 a. ac characteristics temporary sector unprotect: moved the accelerated program timing diagram to follow the program opera- tions timings. added the term sector block where appropriate elsewhere on the page. revision c (january 1998) global changed data sheet title. product selector guide replaced full voltage range: v cc = 2.7C3.6 v with standard voltage range: v cc = 2.7C3.3 v. each part number now has a separate set of speed options. ordering information added 70, 90r, and 120r speed options to the valid combination table. reverted fbga designator back to wc. secsi (secured silicon) sector flash memory region factory locked: secsi sector programmed and pro- tected at the factory: corrected the address range of the esn and distinguished between word and byte modes. operating ranges v cc supply voltages: replaced single voltage range with voltage ranges for standard and regulated devices. revision c+1 (march 19, 1999) secsi (secured silicon) sector flash memory region customer lockable subsection: in the bullets, text should refer to enter secsi sector region command sequence. revision c+2 (june 14, 1999) changed data sheet status to preliminary. revision c+3 (august 9, 1999) global added am29dl164 specifications to the document. ordering information added the 70r speed option for the dl163, deleted the ssop for the dl162. test specifications table the 90 ns speed option is tested at 100 pf loading. revision c+4 (august 23, 1999) ordering information temperature range: added c = commercial (0c to +70c). operating ranges added commercial device. revision c+5 (october 18, 1999) device bus operations autoselect mode: added am29dl164 device ids to the autoselect codes table.
am29dl16xd 51 revision d (february 22, 2000) global the am29dl16x family has migrated to a new 0.23 m process technology, which is indicated by a d in the ordering part number. all references in this docu- ment have been changed to reflect the new process. distinctive characteristics under performance characteristics, the typical ac- celerated programming time was changed to match the ac tables. ac characteristics figure 17, program operations timing; figure 19, chip/sector erase operations: deleted t ghwl and changed oe# waveform to start at high. erase and program operations table; alternate ce# controlled erase and program operations table: changed the typical and maximum specifications for programming time. erase and programming performance in the table, changed the typical and maximum specifi- cations for programming time. the typical and maxi- mum chip programming times in both byte and word modes are reduced. physical dimensions replaced figures with more detailed illustrations. revision d+1 (june 21, 2000) global data sheet designation has changed from advance information to preliminary. deleted references to the 56-pin ssop and the corre- sponding 70r speed option. ordering information added valid combinations for the am29dl164d device in tsop. added valid combinations for the am29dl162d devices in tsop and fbga packages. deleted valid combinations for the 80 ns am29dl164d device in fbga package. device bus operations table 3, sector addresses for top boot sector de- vices: in note below table, corrected last device part number to top boot. table 7, autoselect codes: the secsi sector indicator bit values have changed from 80h and 00h to 81h and 01h, respectively. command definitions table 14, command definitions: the secsi sector in- dicator bit values have changed from 80h and 00h to 81h and 01h, respectively. ac characteristics read-only operations table: changed parameter t df to 16 ns for all speed options. added note 3. revision d+2 (september 4, 2000) deleted remaining references to 80 ns speed option, which was officially removed in revision d+1. cor- rected references to am29dl16xc, which officially changed to am29dl16xd in revision d. revision d+3 (november 22, 2000) global deleted preliminary status from document. added table of contents. revision e (july 2, 2001) added am29dl161d device to data sheet. deleted extended temperature range devices. sector/sector block protection and unprotection noted that sectors are unprotected in parallel. secsi ? (secured silicon) sector flash memory region noted changes for upcoming versions of these de- vices: reduced secsi sector size and deletion of secsi sector erase functionality. current versions of these devices remain unaffected. trademarks copyright ? 2001 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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